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Minimum 2 years of experience in System Verilog HVL SVA Assertions. Must have executed at-least 2 SoC/IP Formal Verification signoff projects. Must have used Synopsys VC Formal , Cadence Jasper or Questa Formal Tools comprehensively
Hands on experience of developing Formal SV assertion/checkers, coverage register, regressions.
· Functional Checks/Assertions based Property coding to verify RTL Structures
· Data Path, Security, Register, Functional Safety and X Prorogation Verification
· Connectivity Checks on IP/SoC connections
· Fault Analysis using Formal Test bench Analyzer
· Formal Coverage and Regressions
|Experience||4 - 8 Years|
|Salary||10 Lac To 30 Lac P.A.|
|Industry||IT Software - System Programming|
|Key Skills||HVL SVA SV Design Verification Engineer Design Engineer|
|Address||No.122/1 And 122/2, Brigade Road, Opp. Brigade Towers|